PhD and MSc Theses

PhD and MSc Theses, since 1988

Advisor PROFESSOR EMERITUS Avinoam Kolodny
Advisor’s Email kolodny@ee.technion.ac.il
Advisor’s Home-Site http://www.ee.technion.ac.il/people/kolodny/
No of theses 44
Department Electrical and Computer Engineering
Department Web Site ece.technion.ac.il/?lang=he
Student’s Name Graduation Year Degree Abstracts Research Name
Morad Tomer 2016 PhD Abstracts Energy- Efficient System Resource Allocation
Zahavi Eitan 2016 PhD Abstracts Forwarding in Computer Cluster Networks
Manevich Ran 2014 PhD Abstracts Centralized Paradigms in Network on Chip Architectures
Ben-Itzhak Yaniv 2014 PhD Abstracts Advanced Heterogeneous NoC Design
Kvatinsky Shahar 2014 PhD Abstracts Memristor-Based Circuits and Architectures
Moiseev Konstantin 2011 PhD Abstracts Optimization of Interconnects in CMOS Nanoscale Technologies
Guz Zvika 2010 PhD The Interplay of Caches and Threads in Chip-Multiprocessors
Walter Isask’har 2010 PhD Abstracts Network on Chip for Future CMP and SoC
Dobkin Rostislav 2009 PhD Abstracts High-Speed Asynchronous Communication for SoC
Morgenshtein Arkadiy 2008 PhD Abstracts Design and Optimization of On-Chip Interconnect
Bolotin Evgeny 2007 PhD Abstracts Network on Chip
Levy Yifat 2016 MSc Abstracts Digital Circuits Design Using Memristors
Stanislavsky Amnon 2013 MSc Abstracts Power Driven Floorplan and Energy Efficient Adders
Izchak Oved 2013 MSc Abstracts The Interaction between Workloads and Micro Architecture in Highly-Parallel Chip Multi-Processors
Polishuk Leon 2013 MSc Abstracts Latency considerations for NoC interconnection fabrics
Cohen Yaron 2012 MSc Abstracts Low Power D/A Converter Design Considerations
Vishnyakov Victorya 2011 MSc Abstracts Inductive Effects in On-Chip Interconnects
Malits Roman 2011 MSc Abstracts The Potential of Global Scheduling to Improve Utilization in Wide SIMD GPGPU Architectures
Abdelhadi Ameer 2011 MSc Abstracts Timing-Driven Variation-Aware Synthesis of Hybrid Mesh/ Tree Clock Distribution Networks
Sizikov Gregory 2011 MSc Abstracts Design and Analysis of integrated voltage regulators
Kouslik Elkin Anna 2010 MSc Abstracts Macro Models for Power Estimation at RT Level in VLSI
Ben-Itzhak Yaniv 2010 MSc Abstracts Performance and Power Aware Thread Allocation for NoC CMP
Zobel Shmuel 2010 MSc Abstracts Power Performance Tradeoffs in Graphics/GPGPU Based Systems
Damishian Chen 2010 MSc Abstracts Stride Based Dead Block Correlation Prefetcher – A New Long-Latency-Tolerant Data Cache Prefetcher
Vaisband Inna 2009 MSc Abstracts Power Efficient Tree-Based Crosslinks for Skew Reduction
Krimer Evgeni 2009 MSc Abstracts Packet-Level Static Timing Analysis for On-Chip Networks
Aizik Yoni 2009 MSc Abstracts Design Considerations for Low Power CMOS Digital Circuits
Sorani Iris 2008 MSc Abstracts Long Instruction Traces and their Usage
Barash Dror 2008 MSc Abstracts Cache Manipulations Improve Multimedia Applications
Sotman Michael 2007 MSc Abstracts Issues in Analysis and Design of Power Delivery Structures in VLSI
Walter Isask’har 2006 MSc Abstracts Quality of Service in Network on-Chip
Kapchits Anastasia 2006 MSc Abstracts Modeling and Design of Network on Chip Interconnects
Behar Michael 2006 MSc Abstracts Characterization of Hot Traces in Modern Processors
Michaely Shay 2005 MSc Abstracts Wire Resizing for Optimal Migration of Microprocessors
Moiseev Konstantin 2005 MSc Abstracts Performance Optimization by Reordering of Interconnect Wires in VLSI
Morad Tomer 2005 MSc Abstracts Data Trace Cache
Moreinis Michael 2004 MSc Abstracts Repeater Insertion in Deep Sub-Micron VLSI Circuits
Magen Nir 2004 MSc Abstracts Power Issues of On-Chip Interconnect in VLSI
Khamaisee Assad 2004 MSc Abstracts Combining Trace Cache with Value Prediction in Microprocessors
Elboim Yaron 2002 MSc A Clock Tuning Circuit for System-on-Chip
Kosyakovsky Oleg 2002 MSc Abstracts Approaches to Managing Trace Cache in Computer Systems
Dolev Noam 2002 MSc Abstracts Integrated Low-Voltage Delta-Sigma Conversion Circuits in Digital CMOS Technology
Milter Oleg 2002 MSc Abstracts Synthesis of CMOS VLSI Circuits Considering Digital Noise Effects
Shchupak George 2002 MSc Abstracts High Speed, Low Power Medium Size Cache Design